Ayav, T.Tuglular, T.Belli, F.Tuğlular, TuğkanAyav, TolgaBilgisayar Mühendisliği Bölümü2023-10-302023-10-3020102978076954087010.1109/SSIRI-C.2010.222-s2.0-77956097952https://doi.org/10.1109/SSIRI-C.2010.22http://65.108.157.135:4000/handle/123456789/61National University of Singapore (NUS);Infocomm Development Authority of Singapore;Reliability SocietyVHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e., they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. © 2010 IEEE.eninfo:eu-repo/semantics/closedAccessModel checkingProgram transformationSynthesizable VHDLTest case generationTimed automataConference Object4653