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Towards test case generation for synthesizable VHDL programs using model checker

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2010

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Bilgisayar Mühendisliği Bölümü
Founded in 1992, our department has been dedicated to expanding and sharing knowledge, producing a line of highly skilled engineers, and inspiring innovation Department of Computer Engineering was founded in 1992 together with the Izmir Institute of Technology and started to admit students for the Master of Science Program. In 1999, the Department moved to the new campus in Gülbahçe-Urla and the undergraduate program commenced in the same year. Computer Engineering Doctorate Program started in 2014. Currently, the number of students admitted to the undergraduate program is 80. The Department of Computer Engineering offers a wide range of selective courses in its curriculum which enables the students to specialize in different areas of computer science and engineering. Our mission is to create a learning environment where academic research activities and projects are carried out in collaboration with the industry. In this atmosphere we aim to train researchers and engineers who are competent in the discipline, have proficiency in problem solving as well as good communication and organizational skills, committed to life-long learning and ethical values and sensitive to social issues.

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Abstract

VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e., they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. © 2010 IEEE.

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National University of Singapore (NUS);Infocomm Development Authority of Singapore;Reliability Society

Keywords

Model checking, Program transformation, Synthesizable VHDL, Test case generation, Timed automata

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2

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2
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SSIRI-C 2010 - 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion -- 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010 -- 9 June 2010 through 11 June 2010 -- Singapore -- 81517

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Start Page

46

End Page

53

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https://doi.org/10.1109/SSIRI-C.2010.22
 http://65.108.157.135:4000/handle/123456789/61

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