Towards test case generation for synthesizable VHDL programs using model checker
| dc.author.scopusid | 13408184500.0 | |
| dc.author.scopusid | 14627984700.0 | |
| dc.author.scopusid | 57200611344.0 | |
| dc.contributor.author | Ayav, T. | |
| dc.contributor.author | Tuglular, T. | |
| dc.contributor.author | Belli, F. | |
| dc.contributor.author | Tuğlular, Tuğkan | |
| dc.contributor.author | Ayav, Tolga | |
| dc.contributor.other | Bilgisayar Mühendisliği Bölümü | |
| dc.date.accessioned | 2023-10-30T08:07:03Z | |
| dc.date.available | 2023-10-30T08:07:03Z | |
| dc.date.issued | 2010 | |
| dc.department | Izmir Institute of Technology İYTE | en_US |
| dc.department-temp | Ayav, T., Dept. of Computer Engineering, Izmir Institute of Technology, Turkey; Tuglular, T., Dept. of Computer Engineering, Izmir Institute of Technology, Turkey; Belli, F., Dept. of Computer Science, Electrical Engineering and Mathematics, University of Paderborn, Germany | en_US |
| dc.description | National University of Singapore (NUS);Infocomm Development Authority of Singapore;Reliability Society | en_US |
| dc.description.abstract | VHDL programs are often tested by means of simulations, relying on test benches written intuitively. In this paper, we propose a formal approach to construct test benches from system specification. To consider the real-time properties of VHDL programs, we first transform them to timed automata and then perform model checking against the properties designated from the specification. Counterexamples returned from the model checker serve as a basis of test cases, i.e., they are used to form a test bench. The approach is demonstrated and complemented by a simple case study. © 2010 IEEE. | en_US |
| dc.identifier.citation | 2 | |
| dc.identifier.doi | 10.1109/SSIRI-C.2010.22 | |
| dc.identifier.endpage | 53 | en_US |
| dc.identifier.isbn | 9780769540870 | |
| dc.identifier.scopus | 2-s2.0-77956097952 | |
| dc.identifier.startpage | 46 | en_US |
| dc.identifier.uri | https://doi.org/10.1109/SSIRI-C.2010.22 | |
| dc.identifier.uri | http://65.108.157.135:4000/handle/123456789/61 | |
| dc.language.iso | en | en_US |
| dc.opencitations.citationcount | 2 | |
| dc.plumx.crossrefcitations | 2 | |
| dc.plumx.mendeleyreaders | 13 | |
| dc.plumx.scopuscitations | 2 | |
| dc.relation.ispartof | SSIRI-C 2010 - 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion -- 4th IEEE International Conference on Secure Software Integration and Reliability Improvement Companion, SSIRI-C 2010 -- 9 June 2010 through 11 June 2010 -- Singapore -- 81517 | en_US |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
| dc.rights | info:eu-repo/semantics/closedAccess | en_US |
| dc.scopus.citedbyCount | 2 | |
| dc.sobiad.citationcount | 0 | |
| dc.subject | Model checking | en_US |
| dc.subject | Program transformation | en_US |
| dc.subject | Synthesizable VHDL | en_US |
| dc.subject | Test case generation | en_US |
| dc.subject | Timed automata | en_US |
| dc.title | Towards test case generation for synthesizable VHDL programs using model checker | en_US |
| dc.type | Conference Object | en_US |
| dspace.entity.type | Publication | |
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