Model Based Testing of VHDL Programs
No Thumbnail Available
Date
2015
Journal Title
Journal ISSN
Volume Title
Publisher
Ieee
Open Access Color
OpenAIRE Downloads
OpenAIRE Views
Abstract
VHDL programs are often validated by means of test benches constructed from formal system specification. To include real-time properties of VHDL programs, the proposed approach first transforms them to concurrently running network of timed automata and then performs model checking on properties taken from the specification. Counterexamples generated by the model checker are used to form a test bench. The approach is validated by a case study composed of a nontrivial application running on a microprocessor. As presented, the approach enables testing both hardware and software at once.
Description
Ayav, Tolga/0000-0003-1426-5694; Tuglular, Tugkan/0000-0001-6797-3913
Keywords
[No Keyword Available]
Turkish CoHE Thesis Center URL
Fields of Science
Citation
0
WoS Q
Scopus Q

OpenCitations Citation Count
0

Sobiad Citation Count
N/A
Source
39th IEEE Annual International Computer Software and Applications Conference Workshops (COMPSAC) -- JUL 01-05, 2015 -- Taichung, TAIWAN
Volume
Issue
Start Page
427
End Page
432
Collections
PlumX Metrics
Captures
Mendeley Readers : 9